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rev. 1.0 8/10 copyright ? 2010 by silicon laboratories si8220/21 si8220/21 0.5 and 2.5 a mp iso drivers with o pto i nput (2.5, 3.75, and 5.0 k v rms ) features applications safety regulatory approvals description the si8220/21 is a high-performance functional upgrade for opto-coupled drivers, such as the hcpl-3120 an d the hpcl-0302 providing 2.5 a of peak output curren t. it utilizes silicon labora tories' proprietary silicon isolation technology, which provides a choice of 2.5, 3.75, or 5.0 kv rms withstand voltages per ul1577. this technology enables higher performance, reduced variation with te mperature and age, tighter part-to- part matching, and superior common-mode rejection compared to opto- isolated drivers. while the input circuit mimics the characteristics of an led, less drive current is required, resulting in increased efficiency. propagation delay time is independent of input drive current, resulting in consistently short propagation time, tighter unit-to-unit variation, and greater input circuit design flexibility. ? functional upgrade for hcpl-0302, hcpl-3120, tlp350, and similar opto-drivers ? 60 ns propagation delay max (independent of input drive current) ? 14x tighter part-to-part matching versus opto-drivers ? 2.5, 3.75, and 5.0 kv rms isolation ? transient immunity ?? 30 kv/s ? under-voltage lockout protection with hysteresis ? resistant to temperature and aging effects ? gate driver supply voltage ?? 6.5 v to 24 v ? wide operating range ?? ?40 to +125 c ? rohs-compliant packages ?? soic-8 narrow body ?? soic-16 wide body ? igbt/ mosfet gate drives ? industrial control systems ? switch mode power supplies ? ups systems ? motor control drives ? inverters ? ul 1577 recognized ?? up to 5000 vrms for 1 minute ? csa component notice 5a approval ?? iec 60950-1, 61010-1, 60601-1 (reinforced insulation) ? vde certification conformity ?? iec 60747-5-2 (vde 0884 part 2) ?? en 60950-1 (reinforced insulation) patent pending pin assignments: see page 19 v ss v dd v o v ss cathode anode nc 1 2 3 4 5 6 7 8 top view nc nc 9 12 11 10 13 14 15 16 nc nc nc nc nc cathode nc nc anode nc 1 2 3 4 5 6 7 8 v o cathode narrow body soic top view v ss v o v dd wide body soic
si8220/21 2 rev. 1.0 functional block diagram si8220/21 nc nc anode cathode led emulator vo vo vdd vss isolator semiconductor-based isolation barrier rf transmitter rf receiver uv lockout
si8220/21 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3. regulatory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. technical descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5.1. device behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5.2. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3. under voltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1. power supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2. layout considerat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3. power dissipation considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 6.4. input circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5. parametric differe nces between si8220/21 and hcpl-0302 and hcpl-3120 opto drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. pin descriptions (narrow-b ody soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. pin descriptions (wide-body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10. package outline: 8-pin narr ow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11. land pattern: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12. package outline: 16-pi n wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 13. land pattern: 16-pi n wide-body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14. top marking: 16-pin wide b ody soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 15. top marking: 8-pin narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
si8220/21 4 rev. 1.0 1. electrical specifications table 1. electrical characteristics 1 v dd =12v or 15v, v ss = gnd, t a = ?40 to +125 c; typical specs at 25 c. parameter symbol test conditions min typ max units dc specifications power supply voltage v dd (v dd ? v ss )6 . 5?2 4v input current (on) i f(on) 5.0 ? 20 ma input current rising edge hysteresis i hys ?0.5?ma input voltage (off) v f(off) measured at anode with respect to cathode. ? 0.6 ? 1.6 v input forward voltage v f measured at anode with respect to cathode. i f =5ma. 1.7 ? 2.5 v output resistance high (source) r oh 0.5 a devices ? 15 ? ? 2.5 a devices ? 2.7 ? output resistance low (sink) r ol 0.5 a devices ? 5.0 ? 2.5 a devices ? 1.0 ? output high current (source) i oh (0.5 a), i f =0 (see figure 2) ?0.3? a (2.5 a), i f =0 (see figure 2) ?1.5? output low current (sink) i ol (0.5 a), i f =10ma, (see figure 1) ?0.5? a (2.5 a), i f =10ma, (see figure 1) ?2.5? high-level output voltage v oh (0.5 a), i out = ?50 ma ? v dd ?0.5 ? v (2.5 a), i out = ?50 ma v dd ?0.1 low-level output voltage v ol (0.5 a), i out =50ma ? 200 ? mv (2.5 a), i out =50ma 50 high-level supply current output open i f =10ma ? 1.2 ? ma low-level supply current output open v f = ?0.6 to +1.6 v ?1.4?ma input reverse voltage bv r i r =10ma. measured at anode with respect to cathode. 0.5 ? ? v input capacitance c in ?10?pf notes: 1. vdd = 12 v for 5, 8, and 10 v uvlo devices; vdd = 15 v for 12.5 v uvlo devices. 2. see "9.ordering guide" on page 21 for more information.
si8220/21 rev. 1.0 5 vdd undervoltage threshold 2 vdd uv+ v dd rising 5 v threshold see figure 8 on page 14. 5.20 5.80 6.30 v 8 v threshold see figure 9 on page 14. 7.50 8.60 9.40 v 10 v threshold see figure 10 on page 14. 9.60 11.1 12.2 v 12.5 v threshold see figure 11 on page 14. 12.4 13.8 14.8 vdd undervoltage threshold 2 vdd uv? v dd falling 5 v threshold see figure 8 on page 14. 4.90 5.52 6.0 v 8 v threshold see figure 9 on page 14. 7.20 8.10 8.70 v 10 v threshold see figure 10 on page 14. 9.40 10.1 10.9 v 12.5 v threshold see figure 11 on page 14. 11.6 12.8 13.8 vdd lockout hysteresis vdd hys uvlo voltage = 5 v ? 280 ? mv vdd lockout hysteresis vdd hys uvlo voltage = 8 v ? 600 ? mv vdd lockout hysteresis vdd hys uvlo voltage = 10 v or 12.5 v ? 1000 ? mv ac specifications propagation delay time to high output level t plh c l = 200 pf ? ? 60 ns propagation delay time to low output level t phl c l = 200 pf ? ? 40 ns output rise and fall time t r , t f (0.5 a), c l = 200 pf ? ? 30 ns (2.5 a), c l = 200 pf ? ? 20 device startup time t start time from v dd =v dd_uv+ to v o ??40s common mode transient immunity cmti input on or off ? 30 ? kv/s table 1. electrical characteristics (continued) 1 v dd =12v or 15v, v ss = gnd, t a = ?40 to +125 c; typical specs at 25 c. parameter symbol test conditions min typ max units notes: 1. vdd = 12 v for 5, 8, and 10 v uvlo devices; vdd = 15 v for 12.5 v uvlo devices. 2. see "9.ordering guide" on page 21 for more information.
si8220/21 6 rev. 1.0 2. test circuits figure 1. iol sink current test circuit figure 2. ioh source current test circuit input 1 f 100 f 10 rsns 0.1 si822x 1 f cer 10 f el vdd = 15 v in_ out_ vss vdd schottky 50 ns 200 ns measure input waveform gnd i f 5 v + _ input 1 f 100 f 10 rsns 0.1 si822x 1 f cer 10 f el vdd = 15 v in_ out_ vss vdd 50 ns 200 ns measure input waveform gnd i f schottky 5 v + _
si8220/21 rev. 1.0 7 3. regulatory information table 2. regulatory information* csa the si822x is certified under csa component acceptanc e notice 5a. for more details, see file 232873. 61010-1: up to 600 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working volt- age. 60601-1: up to 125 v rms reinforced insulation working voltage; up to 380 v rms basic insulation working voltage. vde the si822x is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. 60747-5-2: up to 891 v peak for basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. ul the si822x is certified under ul15 77 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. *note: regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. regulatory certifications apply to 3.75 kv rms rated devices which are production tested to 4.5 kv rms for 1 sec. regulatory certifications apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. for more information, see "9.ordering guide" on page 21.
si8220/21 8 rev. 1.0 table 3. insulation and safety-related specifications parameter symbol test condition value unit wb soic-16 nb soic-8 nominal air gap (clearance) 1 l(io1) 8.0 min 4.9 min mm nominal external tracking (creepage) 1 l(io2) 8.0 min 4.01 min mm minimum internal gap (internal clearance) 0.014 0.014 mm tracking resistance (proof tracking index) pti iec60112 600 600 v erosion depth ed 0.040 0.040 mm resistance (input-output) 2 r io 10 12 10 12 ? capacitance (input-output) 2 c io f = 1 mhz 2.0 1.0 pf input capacitance 3 c i 4.0 4.0 pf notes: 1. the values in this table correspond to the nominal creepage and clearance values as detailed in "12.package outline: 16-pin wide body soic" on page 25, "10.package outline: 8-pin narrow body soic" on page 23. vde certifies the clearance and creepage limits as 8.5 mm minimum for the wb soic-16 package and 4.7 mm minimum for the nb soic-8 package. ul does not impose a clearance and cree page minimum for component level certifications. csa certifies the clearance and creepage limits as 3.9 mm mi nimum for the nb soic-8 and 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the si822x is conver ted into a 2-terminal device. pins 1?8 (1?4, nb soic-8) are shorted together to fo rm the first terminal and pins 9?16 (5?8, nb so ic-8) are shorted togethe r to form the second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground.
si8220/21 rev. 1.0 9 table 4. iec 60664-1 (vde 0844 part 2) ratings parameter test conditions specification nb soic8 wb soic 16 basic isolation group material group i i installation classification rated mains voltages < 150 v rms i-iv i-iv rated mains voltages < 300 v rms i-iii i-iv rated mains voltages < 400 v rms i-ii i-iii rated mains voltages < 600 v rms i-ii i-iii table 5. iec 60747-5-2 insulation characteristics for si822xxc* parameter symbol test condition characteristic unit wb soic-16 nb soic-8 maximum working insulation voltage v iorm 891 560 v peak input to output test voltage v pr method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1375 1050 v peak highest allowable overvoltage (transient overvoltage, t tr =60sec) v tr 6000 4000 v peak pollution degree (din vde 0110, table 1) 22 insulation resistance at t s , v io =500v r s >10 9 >10 9 ? *note: this isolator is suitable for basic electrical isolation only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the si822x prov ides a climate classification of 40/125/21.
si8220/21 10 rev. 1.0 figure 3. (wb soic-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 6. iec safety limiting values 1 parameter symbol test condition min typ max unit wb soic-16 nb soic-8 case temperature t s ? ? 150 150 c safety input, output, or supply current i s ? ja = 140 c/w (nb soic-8), 100 c (wb soic-16), v i =5.5v, t j =150c, t a =25c ?? 50 40 ma device power dissipation 2 p d ?? 1.2 1.2 w notes: 1. maximum value allowed in the event of a failure; also see the thermal derating curve in figures 4 and 5. 2. the si822x is tested with v o =24v, t j =150oc, c l = 200 pf, input a 2 mhz 50% duty cycle square wave. table 7. thermal characteristics parameter symbol min typ max unit wb soic-16 nb soic-8 ic junction-to-air thermal resistance ? ja ? 100 140 ? oc/w 0 200 150 100 50 60 40 20 0 case temperature (oc) safety-limiting current (ma) vdd = 24 v 10 30 50
si8220/21 rev. 1.0 11 figure 4. (nb soic-8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 8. absolute maximum ratings 1 parameter conditions min typ max units storage temperature 2 t stg ?65 ? +150 ? c operating temperature 2 ?40 ? +125 ? c output supply voltage v dd ?0.6 ? 30 v output voltage v o ?0.5 ? v dd + 0.5 v output current drive i o ??10ma input current if (avg) ?100 ? 30 ma lead solder temperature (10 s) ? ? 260 ? c maximum isolation voltage (1 s) nb soic-8 ? ? 4250 v rms maximum isolation voltage (1 s) wb soic-16 ? ? 6500 v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions specified in the operational sections of this data sheet. 2. vde certifies storage temperature from ?40 to 150 c. 0 200 150 100 50 60 40 20 0 case temperature (oc) safety-limiting current (ma) vdd = 24 v 10 30 50
si8220/21 12 rev. 1.0 4. application information 4.1. theory of operation the si8220/21 is a functional upgrade for popular opto-iso lated drivers, such as the avago hpcl-3120, hpcl- 0302, toshiba tlp350, and others. the operation of an si82 20/21 channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified bl ock diagram for the si8220/21 is shown in figure 5. figure 5. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 6 for more details. figure 6. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver led emulator 0.5 to 2.5 a peak gnd v dd input signal output signal modulation signal
si8220/21 rev. 1.0 13 5. technical description 5.1. device behavior truth tables for the si8220/21 are summarized in table 9. 5.2. device startup output v o is held low during power-up until v dd rises above the uvlo+ threshold for a minimum time period of t start . following this, the output is high when the current flowing from anode to cathode is > i f(on) . device startup, normal operation, and shutdown behavior is shown in figure 7. figure 7. si8220/21 operating behavior (i f > i f(min) when v f > v f(min) ) table 9. si8220/21 truth table summary cathode anode diode current (i f )v dd vo comments x x x < uvlo l device turned off hi-z x 0 > uvlo l logic low state x hi-z 0 > uvlo l logic low state gnd gnd 0 > uvlo l logic low state vf vf 0 > uvlo l logic low state gnd1 vf < i f(off > uvlo l logic low state gnd1 vf > i f(off) > uvlo h logic high state note: ?x? = don?t care. this truth table assumes vdd is powered. if vdd is below uvlo, see "5.3.under voltage lockout (uvlo)" on page 14 for more information. i f v o v dd t start t start v ddhys t phl t plh i f(on) uvlo+ uvlo- i hys
si8220/21 14 rev. 1.0 5.3. under voltage lockout (uvlo) the uvlo circuit unconditionally drives v o low when v dd is below the lockout threshold. referring to figures 8 through 11, upon power up, the si8220/21 is maintained in uvlo until vdd rises above vdd uv+ . during power down, the si8220/21 enters uvlo when vdd falls below the uvlo threshold plus hysteresis (i.e., vdd < vdd uv+ ? vdd hys ). figure 8. si8220/21 uvlo response (5 v) figure 9. si8220/21 uvlo response (8 v) figure 10. si8220/21 uvlo response (10 v) figure 11. si8220/21 uvlo response (12.5 v) 3.5 10.5 v dduv+ (typ) output voltage (v o ) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 supply voltage (v dd - v ss ) (v) 6.0 10.5 v dduv+ (typ) output voltage (v o ) 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 supply voltage (v dd - v ss ) (v) 8.5 10.5 v dduv+ (typ) output voltage (v o ) 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 supply voltage (v dd - v ss ) (v) 11.3 10.5 v dduv+ (typ) output voltage (v o ) 11.8 12.3 12.8 13.3 13.8 14.3 14.8 15.3 supply voltage (v dd - v ss ) (v)
si8220/21 rev. 1.0 15 6. applications 6.1. power supply connections v ss can be biased at, above, or below ground as long as the voltage on v dd with respect to v ss is a maximum of 24 v. v dd decoupling capacitors should be placed as close to the package pins as possible. the optimum values for these capacitors depend on load current and the distance between the chip and its power source. it is recommended that 0.1 and 10 f bypass capacitors be used to reduce high-frequency noise and maximize performance. 6.2. layout considerations it is most important to minimize ringing in the drive path and noise on the v dd lines. care must be taken to minimize parasitic inductance in these paths by locating the si8220/21 as close to th e device it is driving as possible. in addition, the v dd supply and ground trace paths must be kept short. for this reason, the use of power and ground planes is highly recommended. a split gr ound plane system having separate ground and v dd planes for power devices and small signal components provides the best ov erall noise performance. 6.3. power dissipation considerations proper system design must assure that the si8220/21 op erates within safe thermal limits across the entire load range. the si8220/21 total power dissipation is the sum of the power dissipated by bias supply current, internal switching losses, and power delivered to the load, as shown in equation 1. equation 1. the maximum allowable power dissipation for the si8220/ 21 is a function of the package thermal resistance, ambient temperature, and maximum allowable ju nction temperature, as shown in equation 2. equation 2. substituting values for p dmax t jmax , t a , and ? ja into equation 2 results in a maximum allowable total power dissipation of 1.0 w. the maximum allowable load is found by substituting this limit and the appropriate datasheet values from table 1 on page 4 into equation 1 an d simplifying. the result is equation 3, where v f =2.8v, i f = 10 ma, and v dd =18v. p d v f ?? i f ?? duty cycle ?? v dd ?? i qout ?? c int ?? v dd 2 ?? f ?? c l ?? v dd 2 ?? f ?? where: p d is the total si8220 device power dissipation (w) i f is the diode current (20 ma max) v f is the diode anode voltage (2.8 v max) i qout is the driver maximum bias curent (5 ma) c int is the internal parasitic capacitance (370 pf) v dd is the driver-side supply voltage (24 v max) f is the switching frequency (hz) ++ + = p dmax t jmax t a ? ? ja --------------------------- where: p dmax is the maximum allowable si8220/21 power dissipation (w) t jmax is the si8220/21 maximum junction temperature (150 c) t a is the ambient temperature (c) ? ja is the si8220/21 package junction-to-a ir thermal resistance (125 c/w) ?
si8220/21 16 rev. 1.0 equation 3. a graph of equation 3 is shown in figure 12. each point along the load line in this graph represents the package dissipation-limited value of c l for the corresponding switching frequency. figure 12. maximum load vs. switching frequency 6.4. input circuit design opto driver manufacturers typically recommend the circ uits shown in figures 13 and 14. these circuits are specifically designed to improve op to-coupler input common-mode rejection and increase noise immunity. figure 13. opto driver input circuit c lmax ?? 1.35 10 3 ? ? f ----------------------------- - 1.85 ? 10 10 ? ? where: c lmax ?? is the maximum load (pf) allowable at switching frequency f = 100 1,000 10,000 0 500 1,000 1,500 2,000 2,500 frequency (khz) load (pf) r1 1 2 3 4 opto driver vdd open drain or collector control input anode cathode n/c n/c
si8220/21 rev. 1.0 17 figure 14. high cmr opto driver input circuit the optically-coupled driver circuit of figure 13 turns the led on when the control input is high. however, internal capacitive coupling from the led to the power and ground conductors can momentarily force the led into its off state when the anode and cathode inputs are subjected to a high common-mode transient. the circuit shown in figure 14 addresses this issue by using a value of r1 suff iciently low to overdrive the led, ensuring it remains on during an input common-mode transient. q1 shorts the led off in the low output state, again increasing common- mode transient immunity. some opto driver applicat ions also recommend reverse-biasing the led when the control input is off to prevent coupled noise from energizing the led. the si8220/21 can be used with the i nput circuits shown in figures 13 and 14; however, some applications will require increasing the value of r1 in order to limit i f to a maximum of 20 ma. the si8220/21 propagation delay and output drive do not change for values of i f between i f(min) and i f(max) . new designs should consider the input circuit configurations of figure 15, which are more effi cient than those of figures 13 and 14. as shown, s1 represents any suitable switch, such as a bjt or mosfet, analog transmission gate, processor i/o, etc. also, note that the si8220/21 input can be driven from the i/o port of any mcu or fpga capable of sourcing a minimum of 5 ma (see figure 15c). figure 15. si8220/21 other input circuit configurations r1 1 2 3 4 opto driver vdd control input anode cathode n/c n/c q1 1 2 3 4 control input +5v r1 s1 si8220/21 n/c anode cathode n/c see text si8220/21 1 2 3 4 +5 v r1 control input s1 n/c anode cathode n/c see text 1 2 3 4 r1 mcu i/o port pin si8220/21 n/c anode cathode n/c a b c
si8220/21 18 rev. 1.0 6.5. parametric differ ences between si8220/21 and hcpl-0302 and hcpl-31 20 opto drivers the si8220/21 is designed to directly replace hcpl-31 20 and similar opto drivers. parametric differences are summarized in table 10 below. 6.5.1. supply voltage and uvlo the supply voltage of the si8220/21 is limited to 24 v, and the uvlo voltage thresholds are scaled accordingly. opto replacement applications should limit their supply voltages to 24 v or less. 6.5.2. input diode differences the si8220/21 input circuit requires less current and has t wice the off-state noise margin compared to opto drivers. however, high cmr opto driver designs that overdrive the led (see figure 14) may require increasing the value of r1 to limit input current to 20 ma max. in addition, there is no benefit in driving the si8220/21 input diode into reverse bias when in the off state. consequently, opto driv er circuits using this tec hnique should either leave the negative bias circuitry unpopulated or modify the circui try (e.g. add a clamp diode) to ensure that the anode pin of the si8220/21 is no more than ?0.8 v with respect to the cathode when reverse-biased. table 10. parametric differences of si8220 vs. hcpl-3120 parameter si8220 hcpl-3120 units max supply voltage 24 30 v on state forward input current 5 to 20 7 to 16 ma off state input voltage ?0.6 to +1.6 ?0.3 to +0.8 v max reverse input voltage 0.5 ?5 v uvlo threshold (rising) 5.8 to 13.8 11.0 to 13.5 v uvlo threshold (falling) 5.5 to 12.8 9.7 to 12.0 v uvlo hysteresis 0.28 to 1 1.6 v rise/fall time into 10 ? in series with 10 nf 20 100 ns table 11. parametric differences of si8221 vs. hcpl-0302 parameter si8221 hcpl-0302 units max supply voltage 24 30 v on state forward input current 5 to 20 7 to 16 ma off state input voltage ?0.6 to +1.6 ?0.3 to +0.8 v max reverse input voltage 0.5 ?5 v uvlo threshold (rising) 5.8 to 13.8 11.0 to 13.5 v uvlo threshold (falling) 5.5 to 12.8 9.7 to 12.0 v uvlo hysteresis 0.28 to 1 1.6 v rise/fall time into 10 ? in series with 10 nf 20 100 ns
si8220/21 rev. 1.0 19 7. pin descriptions (narrow-body soic) figure 16. pin configuration table 12. pin descriptions (narrow-body soic) pin name description 1 nc no connect. 2 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 3 cathode cathode of led emulator. v o follows the signal applied to an ode with respect to this input. 4 nc no connect. 5v ss external mosfet source connection and ground reference for v dd . this terminal is typically connected to ground but may be tied to a negative or positive voltage. 6v o output signal. pins 6 and 7 are connected together internally. 7v o output signal. pins 6 and 7 are connected together internally. 8v dd output-side power supply input referenced to v ss (24 v max). *note: no connect. these pins are not internally connected. nc anode nc 1 2 3 4 5 6 7 8 v o cathode si8220/21 top view v ss v o v dd
si8220/21 20 rev. 1.0 8. pin descriptions (wide-body soic) table 13. pin descriptions (wide-body soic) pin name description 1,7 cathode cathode of led emulator. v o follows the signal applied to anode with respect to this input. 2,3,5,6,8, 10,11,12, 14 nc* no connect. 4 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 9,16 v ss external mosfet source connection and ground reference for v dd . this terminal is typically connected to ground but may be tied to a negative or positive voltage. 13 v o output signal. 15 v dd output-side power supply input referenced to v ss (24 v max). *note: no connect. these pins are not internally connected. v ss v dd v o v ss cathode anode nc 1 2 3 4 5 6 7 8 top view nc nc 9 12 11 10 13 14 15 16 si8220 nc nc nc nc nc cathode nc
si8220/21 rev. 1.0 21 9. ordering guide not all possible device configuration options and their co rresponding ordering part numbers (opn) are included in the ordering guide table. however, if there is a specific de vice configuration of interest that is currently not listed in the ordering guide table, please cont act your local silicon labs sales repr esentative, or go to the silicon labs technical support web page at https://w ww.silabs.com/support/pages/contacttec hnicalsupport.aspx and register to submit a request to create your specific device configuration and opn. figure 17. si8220/21 opn naming convention si82ciuv-r-tpn isodriver product peak output current (0=2.5a, 1=0.5a) uvlo* level (a=5v, b=8v, c=10v, d=12.5v) insulation rating (a=1kv,b=2.5kv,c=3.75kv,d=5kv) product revision temp range (i=-40 to +125c) package type (s=soic) package extension (1=narrow body) *uvlo= under voltage lock out input configuration (2 = opto-input)
si8220/21 22 rev. 1.0 table 14. si8220/21 ordering guide* new ordering part number (opn) ordering options input configuration peak output current (cross reference) uvlo voltage insulation rating temp range pkg type si8220bb-a-is opto input 2.5 a (hcpl-3120) 8v default 2.5 kvrms ?40 to +125 c soic-8 si8220cb-a-is opto input 2.5 a (hcpl-3120) 10 v 2.5 kvrms ?40 to +125 c soic-8 si8220db-a-is opto input 2.5 a (hcpl-3120) 12.5 v 2.5 kvrms ?40 to +125 c soic-8 si8220bd-a-is opto input 2.5 a (hcpl-3120) 8v default 5.0 kvrms ?40 to +125 c wb soic-16 si8220cd-a-is opto input 2.5 a (hcpl-3120) 10 v 5.0 kvrms ?40 to +125 c wb soic-16 si8220dd-a-is opto input 2.5 a (hcpl-3120) 12.5 v 5.0 kvrms ?40 to +125 c wb soic-16 si8221cc-a-is opto input 0.5 a (hcpl-0302) 10 v 3.75 kvrms ?40 to +125 c soic-8 si8221dc-a-is opto input 0.5 a (hcpl-0302) 12.5 v 3.75 kvrms ?40 to +125 c soic-8 *note: all packages are rohs-compliant. moisture sensitivity level is msl3 with peak reflow temper ature of 260 c according to the jedec industry standard classifications and peak solder temperature.
si8220/21 rev. 1.0 23 10. package outline: 8-pin narrow body soic figure 18 illustrates the package details for the si822x. table 15 lists the val ues for the dimensions shown in the illustration. figure 18. 8-pin small outline integrated circuit (soic) package table 15. package diagram dimensions symbol millimeters min max a 1.35 1.75 a1 0.10 0.25 a2 1.40 ref 1.55 ref b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27 bsc h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 ? 0 ? 8 ? ?
si8220/21 24 rev. 1.0 11. land pattern: 8-pin narrow body soic figure 19 illustrates the recommended land pattern details for the si822x in an 8-pin narrow-body soic. table 16 lists the values for the dimens ions shown in the illustration. figure 19. pcb land pattern: 8-pin narrow body soic table 16. pcm land pattern dimensions (8-pin narrow body soic) dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x173-8n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si8220/21 rev. 1.0 25 12. package outline: 16-pin wide body soic figure 20 illustrates the package details for the si822x digital isolator. ta ble 17 lists the values for the dimensions shown in the illustration. figure 20. 16-pin wide body soic table 17. package diagram dimensions symbol millimeters min max a ? 2.65 a1 0.1 0.3 d 10.3 bsc e 10.3 bsc e1 7.5 bsc b 0.31 0.51 c 0.20 0.33 e 1.27 bsc h 0.25 0.75 l 0.4 1.27 ? 0 7
si8220/21 26 rev. 1.0 13. land pattern: 16-pin wide-body soic figure 21 illustrates the reco mmended land pattern details for the si822x in a 16-p in wide-body soic. table 18 lists the values for the dimens ions shown in the illustration. figure 21. 16-pin soic land pattern table 18. 16-pin wide body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si8220/21 rev. 1.0 27 14. top marking: 16-pin wide body soic figure 22. 16-pin wide body soic top marking table 19. 16-pin wide body soic top marking explanation line 1 marking: base part number ordering options see ordering guide for more information. si82 = isodriver product series c = input configuration 2 = opto input type i = peak output current 0 = 2.5a; 1 = 0.5a u = uvlo level a = 5 v; b = 8 v; c = 10 v; d = 12.5 v v = isolation rating a = 1 kv; b = 2.5 kv; c = 3.75 kv d = 5.0 kv line 2 marking: yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. line 3 marking: circle = 1.5 mm diameter (center justified) "e4" pb-free symbol country of origin iso code abbreviation tw = taiwan si82ciuv yywwtttttt tw e4
si8220/21 28 rev. 1.0 15. top marking: 8-p in narrow body soic figure 23. 8-pin narrow body soic top marking table 20. 8-pin narrow body soic top marking explanations line 1 marking: base part number ordering options (see ordering guide for more information) si82 = isodriver product series c = input configuration 2 = opto input type i = peak output current 0=2.5a; 1=0.5a u = uvlo level a = 5 v; b = 8 v; c = 10 v; d = 12.5 v v = isolation rating a = 1 = kv; b = 2.5 = kv; c = 3.75 kv d = 5.0 kv line 2 marking: tttttt manufacturing date code assigned by assembly con- tractor. line 3 marking: circle = 1.1 mm diameter left-justified "e4" pb-free symbol si82ciuv tttttt yyww e4
si8220/21 rev. 1.0 29 d ocument c hange l ist revision 0.22 to revision 1.0 ? updated tables 2, 3, 4, and 5. ? updated ?9. orde ring guide? . ? added device ma rking sections.
si8220/21 30 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. the sale of this product contains no licens es to power-one?s intellectual property. contact power-one, inc. for appropriate lic enses.

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